1. Field of the Invention
This invention relates to a system for performing analog-to-digital ("A/D") conversion and, more particularly to a digital decimation filter which, in part, removes quantization noise produced by a modulator of the A/D converter. The decimation filter includes multiple filter stages, and performs switchable fractional and integer sample data rate reduction of the incoming one bit digital signal while minimizing the complexity of filter stages and the speed by which those filter stages operate.
2. Description of the Related Art
A popular A/D converter includes the oversampled converters or delta-sigma converters. A delta-sigma (or sigma-delta) converter is inherently an oversampling converter, although oversampling is just one of the techniques contributing to its overall performance. Essentially, a delta-sigma converter digitizes an analog signal at a very high sampling rate (i.e., oversampling) to perform a noise-shaping function, and to move the quantization noise to a higher frequency outside the frequency band of interest. The high frequency quantization noise can later be removed by a digital low pass filter. Decimation can thereafter be used to reduce the effective sampling rate back to the "Nyquist" rate.
FIG. 1 illustrates an exemplary third order delta-sigma converter 10. Converter is denoted a third order converter in that the output of A/D quantizer 12 is converted back to analog and then is fed into three sum nodes 16a, 16b and 16c. Integrators 14a, 14b and 14c and coupled as shown subsequent to respective sum nodes 16a, 16b and 16c. The integrators 14 integrate respective outputs of sum nodes 16a and 16b to produce the third order integration function.
The modulator which includes the various integrators 14 performs noise shaping to move its own quantization noise out of the frequency band of interest. The digital low pass filter which follows the modulator serves to eliminate the out-of-band noise without degrading the in-band signal. The modulator performs a sampling function of K times for each cycle of the analog signal A.sub.IN. The output of quantizer 12 is therefore a digital bit stream of 1s and 0s.
A digital-to-analog ("D/A") converter 18 is used to select between a pair of reference voltages depending on whether a 1 or 0 is produced from quantizer 12. Operation of various components within a single or multiple-order delta-sigma modulator is illustrated in reference to U.S. Pat. No. 4,851,841, herein incorporated by reference.
Many modern delta-sigma modulators attempt to minimize overload produced from the modulator by utilizing what is often called a "cascaded" arrangement. A cascaded delta-sigma modulator is defined as one having more than one stage of single- or multiple-order integrators coupled together. An example of a multiple-order stage coupled in cascade with subsequent single or multiple-order stages is illustrated in reference to U.S. Pat. No. 5,654,711, herein incorporated by reference.
Referring to FIGS. 1 and 2 in combination, noise induced by quantizer 12 generally exist at a frequency above the passband fa and upwards to an oversampling ratio K times the Nyquist sampling frequency fs. The integrators 14 produces an out-of-band tail between, e.g., fs/2 and Kfs/2. The digital decimation filter 22 serves to remove the out-of-band tail, quantization noise between fs/2 and Kfs/2, as shown by reference numeral 24. Integrator 14 serves as a high-pass filter to quantization noise and can therefore be viewed as a noise shaping filter.
Utilizing two integrators rather than one improves the signal-to-noise ratio as a function of the oversampling ratio. FIG. 2 indicates that a first order transfer function has a slope 26 of about 6 dB per octave less than slope 28 of a second order transfer function. A careful increase in the number of orders, or cascading multiple orders, helps minimize the amount of noise which falls within a frequency band between zero and fa.
Digital decimation filter 22 must not only filter out the higher frequency noise produced by the noise-shaping process of the delta-sigma modulator, but also must act as an anti-aliasing filter with respect to the final sampling rate fs. Reducing the oversampled data rate to a final sampling rate fs involves digitally sub-sampling the filtered output of the delta-sigma modulator using a process called "decimation". Decimation is generally a well known concept, and can be viewed as a method by which redundant signal information introduced by, e.g., the oversampling process is removed.
In delta-sigma A/D converters, it is quite common to combine the decimation function with the digital filtering transfer function. This results in an increase in computational efficiency if done correctly. There are numerous digital filters which can be implemented with decimation. A popular filter includes the finite impulse response ("FIR") filter, often denoted as a moving weighted average filter. An advantage of FIR filters is that filter outputs need only be computed at the lower decimation rate, thereby achieving considerable efficiency in the computational process. Another filter denoted as the infinite impulse response ("IIR") filter is used if it is acceptable to compute an output for every sampled input. Depending on the amount of complexity needed, FIR and IIR filters can be implemented in multiple stages to achieve an overall digital decimation filter. A general discussion of FIR and IIR filters and/or the use of those filters in multiple stages implemented with multi-rates is set forth in, for example, U.S. Pat. Nos. 5,079,734 and 5,455,782, and further in an article to Franca et al, entitled "Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing", (Prentice Hall, 2.sup.nd Ed., 1994) pp. 251-288 (herein incorporated by reference).
The disadvantage associated with conventional FIR and IIR filters is that they generally require a coefficient multiplier at each of the plurality of taps associated with those structures. Each tap of the FIR and IIR structure requires a somewhat complex multiplier function, and each multiplier may have its own unique weighting factor. Achieving a distinct multiplier ratio for specific taps can require a fairly complex set of multiplier operations. It is therefore desirable that if a digital decimation filter includes FIR and IIR multiplier operations, those operations should be performed only when the data rates are relatively low.
If a portion of the digital decimation filter which receives the faster, oversampled data (i.e., "front-end portion") can somehow be reduced in complexity from that of a back-end portion, post-decimation, the overall decimation filter structure can be improved. Not only should the desired front-end portion avoid FIR and IIR structures, but must do so in multiple stages while expeditiously changing (interpolating and decimating) sampling rates in the interim between those stages to minimize complexity of both the front-end portion and the back-end portion.
In addition to implementing a digital decimation filter as multiple stages of decimation and interpolation, it of a non-conventional, desired benefit to carefully arrange the interpolation and decimation filters within the front-end portion so that the overall digital decimation filter can achieve either an integer sample rate conversion or a fractional sample rate conversion. Conventional digital decimation filters are limited, however, to integer sample rate reduction from Kfs to fs. It would be desirable to introduce a decimation filter which has a front-end portion dedicated to programmable, fractional decimation in order for the decimation filter to accommodate incoming sample rates which cannot be decimated to fs by whole integer numbers. Accordingly, it would be of benefit to implement at least a portion of a decimation filter which can decimate the incoming sampling rate by either integer or fractional amounts and can do so without requiring filter stages which employ coefficient multipliers or other complex scaling operations normally attributed, e.g., to FIR and IIR transfer functions.